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MKY36 HLS Master IC

It is a master IC compatible with HLS. It can be connected to the CPU using an 8 or 16-bit bus for use.

The MKY36 is a center IC (hereinafter referred to as "master") compatible with HLS (Hi-speed Link System). The MKY36 can be connected to the CPU using an 8-bit or 16-bit bus, allowing access from the CPU. Access to the MKY36 from the CPU can be handled similarly to SRAM, enabling the CPU to control communication and DIO simply by reading/writing to the MKY36's memory. The MKY36 has two receiving terminals (RXD1, RXD2), allowing it to control two RS-485 communication lines. Additionally, it is equipped with two interrupt terminals, enabling various interrupt functions such as input update interrupts and communication error occurrence interrupts. Besides these various interrupt functions, the MKY36 also incorporates a communication protocol, achieving communication functionality that reduces the load on the CPU.

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